//------------------------------------------------------------
//  Filename: periph_crg.v
//   
//  Author  : wlduan@gmail.com
//  Revise  : 2019-06-21 23:21
//  Description: 
//   
//  Copyright (C) 2014, YRBD, Inc. 					      
//  All Rights Reserved.                                       
//-------------------------------------------------------------
//
`timescale 1ns/1ps
 
module PERIPH_CRG ( 
    input  wire clk , // 100mhz
    input  wire sys_rstn,

    output wire periphere_rstn,  
    output wire periphere_clk300k,  
    output wire periphere_clk10k,  
    output wire periphere_clk1k
);      
//--------------------------------------------------------
localparam PERIOD_CLK0 = 100000/2;  //1k clk
localparam PERIOD_CLK1 = 10000/2;   //10k clk
localparam PERIOD_CLK2 = 333/2;     //300k clk
//--------------------------------------------------------
wire      rst = ~sys_rstn;
//--------------------------------------------------------
reg[31:0] counter_1k;
reg[31:0] counter_10k;
reg[31:0] counter_300k;
//--------------------------------------------------------
reg       clk300k_out; 
reg       clk10k_out;    
reg       clk1k_out;   
//--------------------------------------------------------
always@(posedge clk ,posedge rst) begin
    if (rst) begin
        counter_1k <= 0;
    end
    else begin
         counter_1k <= (counter_1k > PERIOD_CLK0*2 )? 0:(counter_1k + 1);
    end
end
//--------------------------------------------------------
always@(posedge clk ,posedge rst) begin
    if (rst) begin
        counter_10k <= 0;
    end
    else begin
        counter_10k <= (counter_10k > PERIOD_CLK1*2 )?0:(counter_10k + 1);
    end
end
//--------------------------------------------------------
always@(posedge clk ,posedge rst) begin
    if (rst) begin
        counter_300k  <= 0;
    end
    else begin
         counter_300k <= (counter_300k > PERIOD_CLK2*2 )? 0:(counter_300k + 1);
    end
end
//--------------------------------------------------------
always@(posedge clk ) clk1k_out   <= (counter_1k   > PERIOD_CLK0)?1'b1:1'b0;
always@(posedge clk ) clk10k_out  <= (counter_10k  > PERIOD_CLK1)?1'b1:1'b0;
always@(posedge clk ) clk300k_out <= (counter_300k > PERIOD_CLK2)?1'b1:1'b0;
//--------------------------------------------------------
BUFG inst0(
    .I(clk300k_out),
    .O(periphere_clk300k)
);
//--------------------------------------------------------
BUFG inst1(
    .I(clk10k_out),
    .O(periphere_clk10k)
);
//--------------------------------------------------------
BUFG inst2(
    .I(clk1k_out),
    .O(periphere_clk1k)
);
//--------------------------------------------------------
assign periphere_rstn = sys_rstn;
//--------------------------------------------------------
endmodule
